1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a memory architecture for facilitating storage and access of data in memory cells, such as in thinly capacitively-coupled thyristor (xe2x80x9cTCCTxe2x80x9d) based memory cells.
2. Description of Related Art
Random Access Memories (xe2x80x9cRAMxe2x80x9d) are memories capable of multiple read-write cycles and are widely used to temporally store data in computing applications. A typical RAM is structured to include numerous memory cells arranged in an array of rows and columns wherein each memory cell is designed to store a datum or unit of data as a binary digit (i.e., a binary zero or a binary one). Each row of the memory cell array is typically connected to a word line and each column of the memory cell array is typically connected to a bit line (or a pair of complementary bit lines in an SRAM-based memory). The typical RAM structure also includes other circuitry to effect traditional read and write operations, such as reference signal generation circuitry, signal sensing circuitry, and control signal circuitry.
Reference signal generation circuitry is designed to provide a reference in which to compare a data signal (e.g., voltage or current) representing the unit of data stored in a memory cell. Depending on the memory cell, the reference signal can be a complementary signal, such as in an SRAM device, or an independently derived reference signal, such as in a DRAM device. Independently derived reference signals are generated by memory cells known as reference cells, where reference cells are well known for providing a reliable and accurate reference signal (e.g., reference voltage or current) in which to compare the data signal.
The term xe2x80x9cdevicexe2x80x9d herein is used to describe both a discrete semiconductor circuit element, such as a MOS transistor or a TCCT device, as well as a semiconductor product. A memory semiconductor product can be referred as a memory xe2x80x9cchipxe2x80x9d or xe2x80x9cintegrated circuit (xe2x80x9cICxe2x80x9d)xe2x80x9d and is a circuit element operating cooperatively with other semiconductor products, such as a microprocessor.
Signal sensing circuitry is employed to sense whether the value of the voltage or current representing the unit of data is a logical one or zero. A typical signal sensing circuit is a sense amplifier operating as a differential amplifier. Sense amplifiers (xe2x80x9csense ampsxe2x80x9d or xe2x80x9cSAsxe2x80x9d) are designed to receive the reference signal and the data signal, and thereafter, resolve the data signal into a logical one or zero. Control signal circuitry includes read and write signals to effect such functions and more specifically includes memory address decoding signals, and other signals such as a write driver select control signal.
Not only do RAM memory cells, reference cells and/or sense amplifiers each influence memory architecture design, but three primary design considerations also govern the design thereof. These primary considerations are circuit space, power consumption, and speed, each of which are traditionally traded-off or emphasized at the expense of the others. Such considerations are predominantly governed by the structure and layout of the constituent memory cells, such as SRAM, DRAM and T-RAM cells.
FIGS. 1A and 1B schematically show an SRAM-based memory cell and a DRAM-based memory cell, respectively. FIG. 1A is a general schematic of a typical SRAM memory cell composed of metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) devices A, B in a cross-coupled arrangement with a pair of bit lines (xe2x80x9cBLxe2x80x9d). Devices A are pass transistors designed to operate when an appropriate word line (xe2x80x9cWLxe2x80x9d) signal is applied to the transistor gates. In particular, devices A operate as switches to provide stored data from each cell to one of complementary pair of bit lines BL and BLbar. Devices L are resistors or pull-up transistors to provide appropriate loads to offset charge leakage from the storage transistors represented as devices B. Devices B of FIG. 1A arc storage devices designed to store information as a binary data bit. In a read operation, the word line activates devices A and the SRAM cell provides a stored voltage from a drain of each device B to its respective bit line.
Conventional SRAM chips often employ memory architectures that emphasize two of these primary design considerations at the expense of a third. For example, FIG. 1A is a schematic representation of a conventional SRAM based on a six-transistor (xe2x80x9c6Txe2x80x9d) cell (i.e., two transistors and two resistors plus two cell-access transistors). In another conventional SRAM cell, referred to as a four-transistor (xe2x80x9c4Txe2x80x9d) SRAM cell (not shown), the cell includes four cross-coupled transistors. Such cells are compatible with mainstream CMOS technology, consume relatively low levels of standby power, operate at low voltage levels, and perform at relatively high speeds. Conventional 4T and 6T SRAM cells, however, use a large cell area and thus significantly limit the maximum density of such SRAM cells in an array. Consequently, traditional SRAM memory architectures typically are designed to leverage their high speed and low power characteristics at the cost of additional layout area.
FIG. 1B is a general schematic of a typical DRAM memory cell that includes a MOS device C including a gate connected to a single word line (i.e., row) to enable the cell to store a voltage representing a data bit of information on capacitor CAP. Bit line BL (i.e., column) is used to read data from or to write data to the DRAM cell.
Conventional DRAM chips also employ memory architectures that compromise trade-offs between the three primary design considerations discussed above. DRAM devices, in contrast to SRAM devices, are generally fabricated in arrays with higher densities (i.e., memory cells per unit area) of DRAM cells than SRAM arrays because the individual memory cells of a DRAM include fewer transistors than the individual cells of an SRAM. DRAM cells, unlike SRAM cells, must be periodically refreshed to prevent loss of data. To refresh DRAM cells, additional charge is added to bit lines in a DRAM architecture. The additional charge and bit line capacitance, however, causes read and write operations with DRAM cells to execute at lower speeds than in SRAM memory architectures. Consequently, DRAM memory architectures are designed to provide high cell densities at the expense of speed.
FIG. 1C is a TCCT memory cell as described in U.S. Pat. No. 6,229,161, which is issued to Nemati et al. (xe2x80x9cthe Nemati patentxe2x80x9d) and incorporated herein by reference in its entirety for all purposes. A TCCT based memory cell, alternatively referred to as a T-RAM cell (i.e., Thyristor-RAM), has an xe2x80x9conxe2x80x9d state wherein it generates a current to represent a logic xe2x80x9c1xe2x80x9d that is received by the bit line, and has an xe2x80x9coffxe2x80x9d state wherein it produces essentially no current to represent a logic xe2x80x9c0.xe2x80x9d The TCCT memory cell generally is adapted to operate with two unique word linesxe2x80x94a first word line referred to as word line one (xe2x80x9cWL1xe2x80x9d) and a second word line referred to as word line two (xe2x80x9cWL2xe2x80x9d), both of which include at least one line end referred to herein as a terminus. WL1 is coupled to the gate of access device S, where access device S provides access to storage cell T for transferring bit information between the TCCT memory cell T and the bit line during both read and write operations. WL2 is coupled to TCCT memory cell T and is typically activated only for writing data to the device.
In a proper cell write operation, however, both WL1 and WL2 are activated to transfer a data signal from the bit line to TCCT memory cell T for data storage. To write a logical xe2x80x9c0xe2x80x9d into TCCT cell T, a bit line voltage is raised to a relatively high potential, such as Vdd. Conversely, to write a logical xe2x80x9c1,xe2x80x9d into TCCT cell T, a voltage having a relatively low potential (i.e., 0v or ground) is applied to the bit line. In both cases, WL2 is activated to accomplish writing both logical xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d into the TCCT memory cell T for storage.
It should be noted that if WL2 is enabled without WL1 enabled, such as during a write operation of another cell coupled to the same WL2, a TCCT device""s latching state is most likely affected and thus the previously stored data bit is no longer reliable. In this event, WL1 provides no influence over or control in the write operation of TCCT devices and cannot influence this phenomenon. Therefore, the number of cells coupled to WL2 is a factor in determining an adequate architecture for TCCT-based memory arrays.
TCCT-based memory architectures and their constituent cells, such as the one illustrated in FIG. 1C, provide for the best qualities of both SRAM and DRAM technologies. In particular, TCCT-based memory arrays offer the speed of conventional SRAM-based memory arrays at a cell density equivalent to that achieved by DRAM architectures. Moreover, TCCT-based memory cells are well suited for manufacturing in traditional complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) semiconductor process flows, thus providing for low power memory arrays without a need for complicated (i.e., expensive) semiconductor manufacturing processes.
The memory architectures and structures facilitating the use of the SRAM and DRAM memory cell technologies, however, are not well suited for implementing RAM arrays based on TCCT memory cells without compromising the above three primary design considerations. For example, a drawback to memory architectures using SRAM cells is that they require two bit line signals to provide complementary reference signals. TCCT-based memory arrays, in contrast, sufficiently operate in an open bit line architecture (i.e., higher cell density) because they do not generally require the use of a reference signal based on opposite states of the data stored in the TCCT cell as do SRAM cells. Another drawback to SRAM memory architectures is that they are designed to receive only one word line signal for use during either a read or a write operation and cannot readily accommodate TCCT-based memory cells and their multiple word lines (e.g., WL1 and WL2).
Conventional DRAM devices typically employ folded bit line architectures as illustrated in FIG. 2. In a folded bit line architecture, a single memory array includes memory cells arranged in rows and columns where a memory cell is located at every other intersection of a word line (e.g., W0 through WN) with a bit line, where the bit lines are arranged in complementary bit line pairs, such as Bit0 and Bit0bar. Two rows of reference cells are also included in the array and are addressed through the Ref and Refbar word lines. A first row of reference cells addressable by Ref word line is associated with the Bit0 through BitN bit lines, and a second row of reference cells addressable by the Refbar word line is associated with complementary bit lines Bit0bar through BitNbar. A sense amplifier is coupled to each pair of complementary bit lines for resolving into valid logic levels the voltages developed at one bit line by a memory cell in view of another voltage developed on another bit line by a reference cell.
One of the drawbacks to the folded bit line architecture is that it typically consumes more chip xe2x80x9creal estatexe2x80x9d or die layout area than an open bit line architecture because each alternating intersection 20 does not have a memory cell, as shown in FIG. 2. Another drawback to the folded bit line architecture used by DRAM devices is that it cannot be readily adapted to include TCCT-based memory cells without relaxing the feature size of the TCCT memory cell (i.e., increasing the cell pitch) to include an additional word line. Relaxing a TCCT memory cell would thus increase its size to about twice its optimized size even without configuring the TCCT cell""s word line one and word line two of FIG. 1C to a folded bit line scheme. In yet another drawback to DRAM memory architectures is that they too are designed to receive only one word line signal for use during either a read or a write operation and thus do not readily accommodate TCCT-based memory cells.
A memory architecture capable of using TCCT-based memory cells where the architecture is designed to accommodate other circuitry, such as reference cells and sense amplifiers is a necessity. Such a memory architecture would provide the benefits of each of SRAM and DRAM architectures without the drawbacks described above and other inherent disadvantages of conventional memory architectures. In particular, there is a need for a memory architecture for providing a structure to house TCCT-based memory cells, to provide reference signals and to effectively sense and resolve stored information into a logical value, such as a logical xe2x80x9c0xe2x80x9d or xe2x80x9c1,xe2x80x9d while optimizing each of the primary design considerations of circuit space, power consumption, and speed.
The present invention provides a unique memory architecture especially adapted for TCCT-based memory cells. In accordance with a specific embodiment of the present invention, a memory data block includes a first set of bit lines and a one WL2 line extending to a subset of the first set of bit lines. Such a data block also includes one WL2 driver coupled to the one WL2 line, where the one WL2 driver resides adjacent to the first set of bit lines. Furthermore, a memory cell is located at an intersection of a bit line of the subset of one WL2 lines. In another embodiment, the memory cell is a TCCT-based cell. At least one WL1 line extending to the subset of the first set of one or more bit lines. In yet another embodiment, the data block includes at least one WL1 driver coupled to the at least one WL1 line, the at least one WL1 driver residing adjacent to the first set of one or more bit lines.